This disclosure relates in general to data processing and storage, and more specifically, to management of a non-volatile memory system. Still more particularly, the present disclosure relates to management of a non-volatile memory system to reduce read errors by performing mitigation reads to blocks of non-volatile memory.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology. In a typical implementation, a NAND flash memory array includes multiple physical die, which can each include multiple planes. These planes in turn each contain multiple blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each containing a multiplicity of memory cells. By virtue of the physical arrangement of the word and bit lines utilized to access memory cells, flash memory arrays have generally been programmed on a page basis, but erased on a block basis.
Each memory cell stores one or more bits of data represented by a charge on the floating gate of a transistor or a similar charge trap structure. The amount of charge on the floating gate (or charge trap structure) modulates the threshold voltage of the transistor. By applying a proper read voltage and measuring the amount of current, the programmed threshold voltage of the memory cell can be determined, and thus the stored information can be detected.
Memories storing one, two, three and four bits per cell are respectively referred to in the art as Single Level Cell (SLC), Multi-Level Cell (MLC), Three Level Cell (TLC), and Quad Level Cell (QLC) memories. In multi-level (i.e., MLC, TLC and QLC) NAND flash memory, information is stored by programming the memory cells to various quantized threshold voltage levels according to the device's programming algorithm, which maps the binary bit values to discrete threshold voltage levels. In response to a page read command, the binary bit values are retrieved by applying appropriate read voltages that divide the programmed threshold voltage window into discrete regimes and by then applying a reverse mapping between the detected threshold voltage levels and the corresponding binary bit values.
Over the lifetime of a multi-level NAND flash memory device, the distributions of programmed threshold voltage generally become degraded due to effects such as wear or data retention on the memory cells. In general, the effects of wear on a physical page of memory are manifested through an increase in the bit error rate (BER) observed for the physical page over time. In general, the long-term increase in the BER of the physical pages of a non-volatile memory is addressed by appropriately shifting (either positively or negatively) the read voltage threshold(s) utilizing to distinguish between the possible bit vales stored in the physical pages.